2.1 - Channel Length modulation index

Preview 11:17

2.2 - DC characteristics of Inverter

Preview 35:00

2.3 - Transfer characteristics of Inverter

Preview 28:39

2.4 - Skewed Inverter

Preview 33:18

2.5 - Skewed Inverter and threshold voltage

Preview 17:40

2.6 - Equivalent of transistors in series

Preview 25:52

2.7 - Transmission Gate

Preview 30:40

3.1 - Bad CMOS Buffer - Part1

Preview 24:29

3.2 - Bad CMOS Buffer - Part2

Preview 29:52

3.3 - Noise margin characteristics of inverter

Preview 35:16

3.4 - Noise margin parameters

Preview 17:13

3.5 - Introduction to Delay in CMOS

Preview 27:29

3.6 - Transient analysis of CMOS Inverter

Preview 28:45

3.7 - RC approximated delay

Preview 22:28

3.8 - Switching Resistance

Preview 26:21

4.1 - CMOS Inverter approximated to RC Circuit

Preview 23:51

4.2 - Elmore delay

Preview 34:28

4.3 - Delay of FO4 inverter

Preview 18:18

4.4 - Extracting capacitances of 3-Nand gate for delay estimation

Preview 36:05

4.5 - Characterizing Delay of NOR gate

Preview 35:44

4.6 - Linear Delay model

Preview 23:30

4.7 - Logical effort and Parasitic delay

Preview 33:25

5.1 - Logical effort and Parasitic delay for different gates

Preview 38:34

5.2 - Logical effort for short-channel current model

Preview 25:42

5.3 - Ring Oscillator design

Preview 11:22

5.4 - Optimizing Gate Size

Preview 34:59

5.5 - Optimizing Gate Sizes Example

Preview 24:34

5.6 - Optimizing the Stages for an inverter path

Preview 20:42

5.7 - Optimizing the Stages for a General Circuit

Preview 36:41

5.8 - Decoder Design

Preview 34:14

6.1 - Introduction to Combinational Circuit and assymetric gates

Preview 31:42

6.2 - Assymetric Gates analysis

Preview 14:28

6.3 - Assymetric Gates analysis using short-channel current model

Preview 18:50

6.4 - Introduction to Skewed gates

Preview 24:09

6.5 - Skewed gates and best P/N ratio

Preview 25:33

6.6 - vIntroduction to Pseudo NMOS

Preview 31:07

6.7 - Psudeo NMOS gates

Preview 18:05

6.8 - Other Logic Family

Preview 32:36

6.9 - Dynamic Logic and Domino logic

Preview 22:17

7.1 - Domino gates

Preview 26:36

7.2 - Introduction to Stick Diagram

Preview 35:36

7.3 - Stick Diagram for different gates

Preview 16:00

7.4 - Applying Eulers path for stick diagram representations

Preview 23:14

7.5 - Multiplexer design and layout

Preview 22:13

7.6 - Introduction to Interconnects

Preview 32:02

7.7 - Interconnects - RC delay, and Energy

Preview 22:26

8.1 - Introduction to crosstalks in interconnects

Preview 20:26

8.2 - Transient analysis in Crosstalk

Preview 24:07

8.3 - Introduction to Repeaters in Interconnect Engineering

Preview 30:44

8.4 - Repeater Design

Preview 19:35

8.5 - Energy and delay analysis for interconnectwith repeaters

Preview 14:42

8.6 - Repeater Design and Energy-Delay-Product

Preview 29:15

8.7 - Introduction to Power

Preview 25:58

9.1 - Switching Power and Energy Estimation

Preview 27:44

9.2 - Activity factor and estimating dynamic power for a combinational circuit design

Preview 23:05

9.3 - Analyzing Dynamic Power

Preview 24:06

9.4 - Energy estimation through driving factor

Preview 19:08

9.5 - Energy expression in terms of delay

Preview 30:39

9.6 - Voltage Scaling

Preview 26:36

9.7 - DVFS

Preview 38:54

10.1 - Introduction to subthreshold leakage current model

Preview 35:16

10.2 - Subthreshold leakage current and Gate leakage current

Preview 28:01

10.3 - Estimating Static Power

Preview 21:51

10.4 - Introduction to CMOS Latch design

Preview 36:56

10.5 - CMOS Latch Design

Preview 25:02

10.6 - CMOS Latch and flipflop design

Preview 29:44

11.1 - Static Timing Analysis

Preview 31:41

11.2 - Static Timing Analysis - Continued

Preview 24:13

11.3 - Static Timing Analysis - Part2

Preview 34:26

11.4 - Static Timing Analysis - Part2.1

Preview 10:16

11.5 - Static Timing Analysis - Part3

Preview 29:31

11.6 - TPDQ and TPCQ

Preview 11:36

11.7 - Static Timing Analysis - Part4

Preview 34:05

11.8 - Static Timing Analysis - Part5

Preview 34:54

11.9 - Static Timing Analysis - Part6

Preview 36:00

11.10 - SET and CLEAR enabled Latch and Flipflop Design

Preview 24:20

12.1 - 1-bit Adder design

Preview 27:18

12.2 - Adder-Part2

Preview 25:51

12.3 - PG architecture - Part1

Preview 17:40

12.4 - PG architecture - Part2

Preview 23:08

12.5 - Carry Skip Adder

Preview 31:23

12.6 - Carry Look Ahead and Carry Increment Adder

Preview 32:26

12.7 - Other Adder Subsystems

Preview 26:25

12.8 - Approximate Multipliers - Part 1

Preview 27:20

12.9 - Approximate Multipliers - Part 2

Preview 23:13

12.10 - Approximate Adder

Preview 13:46

Live Session 26-02-2022

Preview 88:05