What you will learn
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Computer Science and Engineering
The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.
Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)
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31:27
Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)
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33:32
Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)
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27:31
Lecture 9: VERILOG OPERATORS
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38:15
Lecture 10:VERILOG MODELING EXAMPLES
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30:41
Lecture 11: VERILOG MODELING EXAMPLES (Contd)
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36:04
Lecture 17:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)
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32:49
Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)
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27:46
Lecture 18:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)
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28:58
Lecture 19:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)
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28:03
Lecture 20:USER DEFINED PRIMITIVES
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31:42
Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)
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31:54
Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)
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26:45
Lecture 27: DATAPATH AND CONTROLLER DESIGN (PART 3)
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30:08
Lecture 28 : SYNTHESIZABLE VERILOG
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31:24
Lecture 29 : SOME RECOMMENDED PRACTICES
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33:22
Lecture 30: MODELING MEMORY
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29:52
Lecture 31: MODELING REGISTER BANKS
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26:46
Lecture 32: BASIC PIPELINING CONCEPTS
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30:26
Lecture 33: PIPELINE MODELING (PART 1)
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27:33
Lecture 34: PIPELINE MODELING (PART 2)
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31:00
Lecture 35: SWITCH LEVEL MODELING (PART 1)
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25:03
Lecture 36: SWITCH LEVEL MODDELING (PART 2)
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25:55
Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)
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26:49
Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)
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28:55
Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)
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31:25
Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)
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30:02
Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)
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35:06
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Meet Your Instructor
About Instructor
VTU is one of the largest Technological Universities in India with 24 years of Tradition of excellence in Engineering & Technical Education, Research and Innovations. It came into existence in the year 1998 to cater the needs of Indian industries for trained technical manpower with practical experience and sound theoretical knowledge.
Free
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Course Duration22 h 15 m 0 s
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Course LevelIntermediate
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Student Enrolled75
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LanguageEnglish
This Course Includes
- 22 h 15 m 0 s Video Lectures
- 0 Quizzes
- 0 Assignments
- 0 Downloadable Resources
- Full Lifetime Access
- Certificate of Completion
Satvik Patil
Dear Professor , I hope this message finds you well. On behalf of the students enrolled in the minor degree program in VLSI Design, I would like to address some concerns we've encountered: Lack of Updates: We have not received any updates regarding the VLSI Design course. Hardware Modeling Verilog: Many of us have applied for this subject, but no quizzes or exams have been scheduled yet. Progress Tracking: Despite completing all the video lectures, our progress is not being reflected in the system. We kindly request that you provide more engaging content for these courses and update the minor degree program to accurately reflect our efforts and progress. Thank you very much for your attention to these matters. Sincerely, Satvik Maruti Patil