Mapping Signal Processing Algorithms to Architectures

Mapping Signal Processing Algorithms to Architectures

@VTU COE

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What you will learn

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Digital Signal Processing typically involves repetitive computations being performed on streams of input data, subject to constraints such as sampling rate or desired throughput. Often such systems need to be implemented under tight constraints on factors such as timing, resources, power or cost. When they are used in embedded systems, it is often worth the effort to design custom architectures that have much better cost tradeoffs than general purpose computing architectures. This course deals with the analysis of such algorithms, and mapping them to architectures that are either custom designed or have specific extensions that make them better suited to certain kinds of operations. Topics covered include fundamental bounds on performance, mapping to dedicated and custom resource shared architectures, and techniques for automating the process of scheduling. Aspects of architectures such as memory access, shared buses, and memory mapped accelerators will be studied. Assignments will cover various aspects of the design process, starting from implementing and testing specifications, to synthesis and scheduling using high level synthesis tools, and analyzing and improving the resulting architectures.

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Meet Your Instructor

Instructor
3.2 Rating
5446 Students
800 Courses
About Instructor

VTU is one of the largest Technological Universities in India with 24 years of Tradition of excellence in Engineering & Technical Education, Research and Innovations. It came into existence in the year 1998 to cater the needs of Indian industries for trained technical manpower with practical experience and sound theoretical knowledge.

video

Free

  • Course Duration
    29 h 38 m 39 s
  • Course Level
    Intermediate
  • Student Enrolled
    0
  • Language
    English
This Course Includes
  • 29 h 38 m 39 s Video Lectures
  • 0 Quizzes
  • 0 Assignments
  • 0 Downloadable Resources
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  • Certificate of Completion