VLSI Design Flow: RTL to GDS

VLSI Design Flow: RTL to GDS

@VTU COE

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What you will learn

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This course covers the entire RTL to GDS VLSI design flow, going through various stages of logic synthesis, verification, physical design, and testing. Besides covering the fundamentals of various design tasks, this course will develop skills in modern chip design with the help of activities and demonstrations on freely available CAD tools. This course will enhance the employability of the students and will make them ready to undertake careers in the semiconductor industry.

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Overview of VLSI Design Flow - III
Preview 43:01
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Overview of VLSI Design Flow - IV
Preview 54:43
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Overview of VLSI Design Flow - V
Preview 59:17
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Overview of VLSI Design Flow - VI
Preview 28:43
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Introduction to TCL
Preview 10:38

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Hardware Modeling: Introduction to Verilog-I
Preview 46:11
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Hardware Modeling: Introduction to Verilog-II
Preview 48:27
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Functional Verification using Simulation
Preview 64:57
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High-level synthesis using Bambu - Tutorial 3
Preview 07:14

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RTL Synthesis- Part I
Preview 55:10
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RTL Synthesis- Part II
Preview 35:02
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Logic Optimization: Part I
Preview 70:51
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Simulation-based Verification using Icarus
Preview 15:40

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Logic Optimization: Part II
Preview 69:46
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Logic Optimization: Part III
Preview 33:48
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Formal Verification-I
Preview 67:15
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Logic Synthesis using Yosys
Preview 07:34

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Formal Verification-II
Preview 34:22
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Formal Verification-III
Preview 64:02
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Formal Verification-IV
Preview 39:54
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Technology Library
Preview 62:32
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Logic Optimization using Yosys
Preview 14:46

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Static Timing Analysis- I
Preview 52:40
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Static Timing Analysis- II
Preview 74:16
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Static Timing Analysis- III
Preview 60:38
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Static Timing Analysis using OpenSTA
Preview 14:07

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Constraints I
Preview 54:44
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Constraints II
Preview 38:55
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Technology Mapping
Preview 30:35
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Timing-driven Optimization
Preview 49:32
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Technology Library and Constraints
Preview 18:05

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Power Analysis
Preview 47:16
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Power Optimization
Preview 37:47
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Basic Concepts of DFT
Preview 51:57
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Scan Design Flow
Preview 42:18
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Power Analysis using OpenSTA
Preview 17:49

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Automatic Test Pattern Generation (ATPG)
Preview 47:05
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Built-in Self Test (BIST)
Preview 45:56
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Basic Concepts for Physical Design - I
Preview 61:41
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Basic Concepts for Physical Design - II
Preview 36:48
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Installation of OpenRoad
Preview 06:05

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Chip Planning - I
Preview 60:43
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Chip Planning - II
Preview 51:33
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Placement
Preview 43:19
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Chip Planning and Placement
Preview 12:24

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Clock Tree Synthesis (CTS)
Preview 48:28
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Routing
Preview 64:43
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Post-layout Verification and Signoff
Preview 44:30
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Clock Tree Synthesis (CTS) and Routing
Preview 13:32

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Live Session 03-10-2023
Preview 90:21
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Meet Your Instructor
@VTU COE
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Instructor
3.2 Rating
5446 Students
800 Courses
About Instructor

VTU is one of the largest Technological Universities in India with 24 years of Tradition of excellence in Engineering & Technical Education, Research and Innovations. It came into existence in the year 1998 to cater the needs of Indian industries for trained technical manpower with practical experience and sound theoretical knowledge.

video

Free

  • Course Duration
    39 h 2 m 29 s
  • Course Level
    Intermediate
  • Student Enrolled
    0
  • Language
    English
This Course Includes
  • 39 h 2 m 29 s Video Lectures
  • 0 Quizzes
  • 0 Assignments
  • 0 Downloadable Resources
  • Full Lifetime Access
  • Certificate of Completion