VLSI Design Flow: RTL to GDS

VLSI Design Flow: RTL to GDS

@VTU COE

0.0
(0) 0 Students
Download Brochure

What you will learn

  • None

This course covers the entire RTL to GDS VLSI design flow, going through various stages of logic synthesis, verification, physical design, and testing. Besides covering the fundamentals of various design tasks, this course will develop skills in modern chip design with the help of activities and demonstrations on freely available CAD tools. This course will enhance the employability of the students and will make them ready to undertake careers in the semiconductor industry.

play
Overview of VLSI Design Flow - III
Preview 43:01
play
Overview of VLSI Design Flow - IV
Preview 54:43
play
Overview of VLSI Design Flow - V
Preview 59:17
play
Overview of VLSI Design Flow - VI
Preview 28:43
play
Introduction to TCL
Preview 10:38

play
Hardware Modeling: Introduction to Verilog-I
Preview 46:11
play
Hardware Modeling: Introduction to Verilog-II
Preview 48:27
play
Functional Verification using Simulation
Preview 64:57
play
High-level synthesis using Bambu - Tutorial 3
Preview 07:14

play
RTL Synthesis- Part I
Preview 55:10
play
RTL Synthesis- Part II
Preview 35:02
play
Logic Optimization: Part I
Preview 70:51
play
Simulation-based Verification using Icarus
Preview 15:40

play
Logic Optimization: Part II
Preview 69:46
play
Logic Optimization: Part III
Preview 33:48
play
Formal Verification-I
Preview 67:15
play
Logic Synthesis using Yosys
Preview 07:34

play
Formal Verification-II
Preview 34:22
play
Formal Verification-III
Preview 64:02
play
Formal Verification-IV
Preview 39:54
play
Technology Library
Preview 62:32
play
Logic Optimization using Yosys
Preview 14:46

play
Static Timing Analysis- I
Preview 52:40
play
Static Timing Analysis- II
Preview 74:16
play
Static Timing Analysis- III
Preview 60:38
play
Static Timing Analysis using OpenSTA
Preview 14:07

play
Constraints I
Preview 54:44
play
Constraints II
Preview 38:55
play
Technology Mapping
Preview 30:35
play
Timing-driven Optimization
Preview 49:32
play
Technology Library and Constraints
Preview 18:05

play
Power Analysis
Preview 47:16
play
Power Optimization
Preview 37:47
play
Basic Concepts of DFT
Preview 51:57
play
Scan Design Flow
Preview 42:18
play
Power Analysis using OpenSTA
Preview 17:49

play
Automatic Test Pattern Generation (ATPG)
Preview 47:05
play
Built-in Self Test (BIST)
Preview 45:56
play
Basic Concepts for Physical Design - I
Preview 61:41
play
Basic Concepts for Physical Design - II
Preview 36:48
play
Installation of OpenRoad
Preview 06:05

play
Chip Planning - I
Preview 60:43
play
Chip Planning - II
Preview 51:33
play
Placement
Preview 43:19
play
Chip Planning and Placement
Preview 12:24

play
Clock Tree Synthesis (CTS)
Preview 48:28
play
Routing
Preview 64:43
play
Post-layout Verification and Signoff
Preview 44:30
play
Clock Tree Synthesis (CTS) and Routing
Preview 13:32

play
Live Session 03-10-2023
Preview 90:21
img
No Discussion Found

0.0

0 Reviews

5
0
4
0
3
0
2
0
1
0
Meet Your Instructor
@VTU COE
img

Instructor
3.2 Rating
2542 Students
759 Courses
About Instructor

VTU is one of the largest Technological Universities in India with 24 years of Tradition of excellence in Engineering & Technical Education, Research and Innovations. It came into existence in the year 1998 to cater the needs of Indian industries for trained technical manpower with practical experience and sound theoretical knowledge.

video

Free

  • Course Duration
    39 h 2 m 29 s
  • Course Level
    Intermediate
  • Student Enrolled
    0
  • Language
    English
This Course Includes
  • 39 h 2 m 29 s Video Lectures
  • 0 Quizzes
  • 0 Assignments
  • 0 Downloadable Resources
  • Full Lifetime Access
  • Certificate of Completion